View L7C108_8586234.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 nc a 16 a 14 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 dq 1 dq 2 dq 3 v ss v cc a 15 ce 2 we a 13 a 8 a 9 a 11 oe a 10 ce dq 8 dq 7 dq 6 dq 5 dq 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 nc a 16 a 14 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 dq 1 dq 2 dq 3 v ss v cc a 15 ce 2 we a 13 a 8 a 9 a 11 oe a 10 ce dq 8 dq 7 dq 6 dq 5 dq 4 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 30 top view 31 14 19 20 4 32 31 2 15 16 17 18 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 dq 1 we a 13 a 8 a 9 a 11 oe a 10 ce 1 dq 8 a 2 a 1 a 0 nc v cc a 16 nc dq 2 dq 3 v ss dq 4 dq 5 dq 6 dq 7 logic devices incorporated www.logicdevices.com 1 aug 11, 2010 lds-L7C108/9-f 1m static rams 128k x 8 static ram L7C108 preliminary information l7c109 128k x 8 static ram with chip select powerdown, output enable and single or dual chip selects high speed ? to 15 ns maximum operational power, -l version active: 140 ma at 15 ns standby: 1 ma max data retention at 2 v for battery backup operation screened to mil-std-883, class b or to smd 5962-89598 package styles available: 32-pin ceramic 400mil dip d12 32-pin ceramic lcc k11 32-pin ceramic so 1 32-pin uad ceramic lcc ka1 pin configuration features 32-pin ceramic dip 32-pin ceramic soj 32-pin quad clcc 32-pin ceramic lcc the L7C108 and l7c109 are high-perfor- mance, low-power cmos static rams. the storage circuitry is organized as 131,072 words by 8 bits per word. the 8 data in and data out signals share i/o pins. the L7C108 has a single active- low chip enable. the l7c109 has two chip enables one active-low . these devices are available in three speeds with maximum access times from 15 ns to 45 ns. inputs and outputs are ttl compatible. operation is from a single +5 v power supply. power consumption is 140 ma -l version at 15 ns. data may be retained in inactive storage with a supply voltage as low as 2 v. the L7C108 and l7c109 provide asyn- chronous unclocked operation with matching access and cycle times. the chip enables and a three-state i/o bus with a separate output enable control simplify the connection of several chips for increased storage capacity. memory locations are specified on address pins a 0 through a 16 . for the L7C108, reading from a designated location is accomplished by present- ing an address and driving ce 1 and oe low while we remains high. for the l7c109, ce 1 and oe must be low while ce 2 and we are high.the data in the addressed memory location will then appear on the data out pins within one access time. the output pins stay in a high-impedance state when ce 1 or oe is high, or ce 2 l7c109 or we is low. writing to an addressed location is accomplished when the active-low ce 1 and we inputs are both low, and ce 2 l7c109 is high. any of these signals may be used to terminate the write oper- ation. data in and data out signals have the same polarity. latchup and static discharge protection are provided on-chip. the L7C108 and l7c109 can withstand an injection cur- rent of up to 200 ma on any pin without damage. overview
standby i cc2 standby i cc2 standby i cc3 standby i cc3 active active active logic devices incorporated www.logicdevices.com aug 11, 2010 lds-L7C108/9-f 1m static rams 2 128k x 8 static ram L7C108 preliminary information l7c109 9 row select we row address i/o 7 - 0 column select & column sense control 8 column address 8 ce1 oe ce2 (l7c109 only) 128 k x 8 memory array L7C108-109 block diagram mode oe ce1 ce2* we dq p ower standby standby standby standby read read write t ruth t able * note: for l7c109 only x x x x l h x t v ih x t v cc - 0.2 v x l l l x d v il x d g nd + 0.2 v h h h x x x x h h l high - z high - z high - z high - z high - z d
logic devices incorporated www.logicdevices.com 3 aug 11, 2010 lds-L7C108/9-f 1m static rams 128k x 8 static ram L7C108 preliminary information l7c109 supply voltage 4.5 v d v cc d 5.5 v 2.0 v d v cc d 5.5 v mode active, operation, military data retention, military o perating c onditions to meet specified electrical and switching characteristics temperature range (ambient) -55c to +125c -55c to +125c m aximum r atings above which useful life may be impaired (notes 1, 2) storage temperature????????????????...?.??............?? operating ambient temperature???????????????......?.......? vcc supply voltage with respect to ground?????.????????.......?. input signal with respect to ground.??????????.??????..?..? signal applied to high impedance output??????????????........? output current into low outputs????????????????.?......................?? latchup current?.........................?????..??????????...??................ -65c to +150c -55c to +125c -0.5 v to +7.0 v -3.0 v to +7.0 v -3.0 v to +7.0 v 25 ma >200 ma L7C108/109 L7C108/109-l symbol parameter test condition min max min max unit v oh v ol v ih v il i ix i oz i cc2 i cc3 i cc4 c in c out output high voltage output low voltage input high voltage input low voltage input leakage current output leakage current v cc current, ttl standby v cc current, cmos standby v cc current, data retention input capacitance output capacitance v cc = 4.5v, i oh = -4 ma i ol = 8 ma note 3 gnd < v in < v cc note 4 note 7 note 8 v cc = 2 v notes 9, 10 ambient temp = 25c, v cc = 5 v test fre uency = 1 mhz note 10 2.4 2.2 -0.5 -10 -10 0.4 v cc +0.5 0.8 +10 +10 25 10 - 8 8 e lectrical c haracteristics over operating conditions (note 5) 2.4 2.2 -3.0 -10 -10 0.4 v cc +0.3 0.8 +10 +10 25 5 0.75 8 8 v v v v a a ma ma ma pf pf symbol parameter test condition L7C108/109-l i cc1 v cc current, active note 6 ma L7C108/109 15 140 20 140 25 140 35 135 45 125 15 140 20 140 25 140 35 130 45 125 unit
logic devices incorporated www.logicdevices.com aug 11, 2010 lds-L7C108/9-f 1m static rams 4 128k x 8 static ram L7C108 preliminary information l7c109 switching characteristics over operating range r ead c ycle notes 5, 11, 12, 22, 23, 24 (ns) L7C108/109 r ead c ycle - a ddress c ontrolled notes 13, 14 data out t avav t pu t pd t elqv high impedance ce oe t elqx t glqv t glqx data valid icc 50% 50% t ghqz t ehqz high impedance r ead c ycle - ce/oe c ontrolled n otes 13, 15 address data out previous data valid i cc t avav t pu t avqx t pd t avqv data valid symbol parameter read cycle time address valid to output valid notes 13, 14 address change to output change chip enable low to output valid notes 13, 15 chip enable low to output low z notes 20, 21 chip enable high to output high z notes 20, 21 output enable low to output valid output enable low to output low z notes 20, 21 output enable high to output high z notes 20, 21 input transition to power up notes 10, 19 15/15-l 20/20-l 25/25-l 35/35-l 45/45-l t avav t av v t av x t el v t el x t eh z t gl v t gl x t gh z t pu min 15 3 3 0 0 max 15 15 7 8 6 min 20 3 3 0 0 max 20 20 8 10 6 min 25 3 3 0 0 max 25 25 10 10 10 min 35 3 3 0 0 max 35 35 15 15 15 min 45 3 3 0 0 max 45 45 20 20 20
logic devices incorporated www.logicdevices.com 5 aug 11, 2010 lds-L7C108/9-f 1m static rams 128k x 8 static ram L7C108 preliminary information l7c109 switching characteristics over operating range r ead c ycle notes 5, 11, 12, 22, 23, 24 (ns) L7C108/109 symbol parameter 15/15-l 20/20-l 25/25-l 35/35-l 45/45-l t pd t cdr operation recovery time notes 10, 19 chip enable high to data retention note 10 data retention mode v cc t cdr 4.5 v 4.5 v 2 v ce v ih t pd v ih d ata r etention notes 9, 10 w rite c ycle notes 5, 11, 12, 22, 23, 24 (ns) L7C108/109 symbol parameter write cycle time chip enable low to end of write cycle address valid to beginning of write cycle address setup to end of write cycle address hold after end of write write enable pulse width low data setup to end of write cycle data hold to end of write write enable high to output low z notes 20, 21 write enable low to output high z notes 20, 21 15/15-l 20/20-l 25/25-l 35/35-l 45/45-l t avav t elwh t avwl t avwh t whax t wlwh t dvwh t whdx t wh x t wl z min 0 min 0 min 0 min 0 min 0 max 15 max 20 max 25 max 35 max 45 min 15 12 0 15 0 12 7 0 5 min 20 12 0 17 0 15 10 0 5 min 25 20 0 20 0 20 12 0 5 min 35 25 0 25 0 30 20 0 5 min 45 35 0 35 0 40 20 0 5 max 7 max 8 max 10 max 25 max 30
address data out ce t avav t avwl t elwh data -in valid t avwh data in icc t pu t pu t wlwh t dvwh t whax t whdx t wlqz high impedance t pd t whqx we data-in valid address data in high impedance t avwl we t avav t aelwh t avwh t wlwh t dvwh t whdx t whax t pd t pu ce i cc data out logic devices incorporated www.logicdevices.com aug 11, 2010 lds-L7C108/9-f 1m static rams 6 128k x 8 static ram L7C108 preliminary information l7c109 switching characteristics over operating range w rite c ycle - we c ontrolled notes 16, 17, 18, 19 w rite c ycle - ce c ontrolled notes 16, 17, 18, 19
logic devices incorporated www.logicdevices.com aug 11, 2010 lds-L7C108/9-f 1m static rams 7 128k x 8 static ram L7C108 preliminary information l7c109 package information 0.825 0.008 pin 1 identifier 0.400 0.005 see detail a 0.025 0.003 0.050 typ 0.085 0.008 0.006 ~ 0.22 typ 0.003 ~ 0.015 detail a 0.070 0.007 0.050 typ 0.055 0.006 0.082 0.0083 pkg k: 32l c eramic d ual lcc (md-k11) *all measurements in inches smd 5962-89598 case ?u? / ordering code ?k?
logic devices incorporated www.logicdevices.com aug 11, 2010 lds-L7C108/9-f 1m static rams 8 128k x 8 static ram L7C108 preliminary information l7c109 package information detail a 0.400 0.005 0.300 0.005 0.550 0.450 see detail a 0.085 0.008 0.050 typ + 0.008 - 0.005 0.025 0.003 0.050 0.005 0.008r 0.020 0.002 0.065 0.006 + 0.10 - 0.05 0.0821 0.0073 pkg ka: 32l c eramic q uad lcc (md-ka1) *all measurements in inches smd 5962-89598 case ?m? / ordering code ?ka?
logic devices incorporated www.logicdevices.com aug 11, 2010 lds-L7C108/9-f 1m static rams 9 128k x 8 static ram L7C108 preliminary information l7c109 package information 32 17 16 1 0.132 0.0203 0.750 0.007 0.050 bsc 0.012 0.0013 0.005 typ 0.822 0.008 0.445 max 0.425 0.006 chamfer 0.020 ref 0.370 0.010 0.035r typ 0.010 ref 0.005 min 0.038 typ 0.025 ref 0.075 ref 0.035 0.010 0.0205 0.091 0.025 0.003 typ 0.017 0.002 pkg y: 32l c eramic soj (md-y1) *all measurements in inches smd 5962-89598 case ?y? and ?7? / ordering code ?y? (note: case ?y? ships for case ?7? as compatible replacement)
logic devices incorporated www.logicdevices.com aug 11, 2010 lds-L7C108/9-f 1m static rams 10 128k x 8 static ram L7C108 preliminary information l7c109 package information 0.05 0.0775 0.135 0.005 1.600 0.016 0.018 0.002 0.050 0.002 typ 0.170 0.005 0.22 0.015 0.050 0.010 0.378 0.005 0.400 0.005 0.010 base plane seating plane lead location guage plane 0.100 0.05 typ + 0.002 - 0.001 0.1471 0.0063 0.317 0.011 pkg d: 32l c eramic dip (md-d12) *all measurements in inches smd 5962-89598 case ?z? / ordering code ?d?
l7c109dmb45 5962-8959835mza L7C108dmb45 5962-8959827mza l7c109dmb35 5962-8959836mza L7C108dmb35 5962-8959828mza l7c109dmb25 5962-8959837mza L7C108dmb25 5962-8959829mza l7c109dmb20 5962-8959838mza L7C108dmb20 5962-8959839mza l7c109dmb15 5962-8959841mza L7C108dmb15 5962-8959844mza l7c109ymb45 5962-8959835m7a L7C108ymb45 5962-8959827m7a l7c109ymb35 5962-8959836m7a L7C108ymb35 5962-8959828m7a l7c109ymb25 5962-8959837m7a L7C108ymb25 5962-8959829m7a l7c109ymb20 5962-8959838m7a L7C108ymb20 5962-8959839m7a l7c109ymb15 5962-8959841m7a L7C108ymb15 5962-8959844m7a l7c109ymb45 5962-8959835mya L7C108ymb45 5962-8959827mya l7c109ymb35 5962-8959836mya L7C108ymb35 5962-8959828mya l7c109ymb25 5962-8959837mya L7C108ymb25 5962-8959829mya l7c109ymb20 5962-8959838mya L7C108ymb20 5962-8959839mya l7c109ymb15 5962-8959841mya L7C108ymb15 5962-8959844mya l7c109kamb45 5962-8959835mma l7c109kamb35 5962-8959836mma l7c109kamb25 5962-8959837mma l7c109kamb20 5962-8959838mma l7c109kamb15 5962-8959841mma l7c109kmb45 5962-8959835mua l7c109kmb35 5962-8959836mua l7c109kmb25 5962-8959837mua l7c109kmb20 5962-8959838mua l7c109kmb15 5962-8959841mua logic devices incorporated www.logicdevices.com aug 11, 2010 lds-L7C108/9-f 1m static rams 11 128k x 8 static ram L7C108 preliminary information l7c109 smd cross reference table logic part # logic part # smd part # smd part #
logic devices incorporated www.logicdevices.com aug 11, 2010 lds-L7C108/9-f 1m static rams 12 128k x 8 static ram L7C108 preliminary information l7c109 smd cross reference table logic part # logic part # smd part # smd part # l7c109dmb45l 5962-8959818mza L7C108ymb45l 5962-8959810m7a l7c109dmb35l 5962-8959819mza L7C108ymb35l 5962-8959811m7a l7c109dmb25l 5962-8959820mza L7C108ymb25l 5962-8959812m7a l7c109dmb20l 5962-8959821mza L7C108ymb20l 5962-8959840m7a l7c109ymb45l 5962-8959818m7a L7C108ymb15l 5962-8959848m7a l7c109ymb35l 5962-8959819m7a L7C108yamb45l 5962-8959810mya l7c109ymb25l 5962-8959820m7a L7C108ymb35l 5962-8959811mya l7c109ymb20l 5962-8959821m7a L7C108ymb25l 5962-8959812mya l7c109ymb45l 5962-8959818mya L7C108ymb20l 5962-8959840mya l7c109ymb35l 5962-8959819mya L7C108ymb15l 5962-8959848mya l7c109ymb25l 5962-8959820mya l7c109ymb20l 5962-8959821mya l7c109kamb45l 5962-8959818mma l7c109kamb35l 5962-8959819mma l7c109kamb25l 5962-8959820mma l7c109kamb20l 5962-8959821mma l7c109kmb45l 5962-8959818mua l7c109kmb35l 5962-8959819mua l7c109kmb25l 5962-8959820mua l7c109kmb20l 5962-8959821mua l7c109fmb20l 5962-8959821mta L7C108dmb45l 5962-8959810mza L7C108dmb35l 5962-8959811mza L7C108dmb25l 5962-8959812mza L7C108dmb20l 5962-8959840mza L7C108dmb15l 5962-8959848mza
l 7c 108 d m b 15 l indicates a logic devices product sram part number: 108 = 1m sram with single chip enable (available in packages d and y) 109 = 1m sram with dual chip enables (available in all packages) package code : d = 32 pin sidebrazed dip 400mil k = 32 pin ceramic lcc ka = 32 pin quad ceramic lcc y = 32 pin ceramic soj screening level: m = milita ry te mp e r atu r e , -55 oc to +125 oc e = e x tended te mp e r atu r e , -40 oc to +105 oc i = indust r ial te mp e r atu r e , -40 oc to +85 oc compliance: b = mil-std-883 co mp liant speed grade: low power option: l = lo w po w e r no ma rk means standa r d po w e r [ m ]: 15 / 20 / 25 / 35 / 45 [ e ]: 15 / 20 / 25 / 35 / 45 [ i ]: 15 / 20 / 25 / 35 / 45 logic devices incorporated www.logicdevices.com aug 11, 2010 lds-L7C108/9-f 1m static rams 13 128k x 8 static ram L7C108 preliminary information l7c109 ordering information
logic devices incorporated www.logicdevices.com 14 aug 11, 2010 lds-L7C108/9-f 1m static rams 128k x 8 static ram L7C108 preliminary information l7c109 n otes 1. maximum ratings indicate stress specifica- tions only. functional operation of these products at values beyond those indicated in the operat- ing conditions table is not implied. exposure to maximum rating conditions for extended periods may affect reliability of the tested device. 2. the products described by this specifica- tion include internal circuitry designed to pro- tect the chip from damaging substrate injection currents and accumulations of static charge. nevertheless, conventional precautions should be observed during storage, handling, and use of these circuits in order to avoid exposure to excessive electrical stress values. 3. this product provides hard clamping of tran- sient undershoot. input levels below ground will be clamped beginning at ?0.6 v. a current in excess of 100 ma is required to reach ?2.0 v. the device can withstand indefinite operation with inputs as low as ?3 v subject only to power dissipation and bond wire fusing constraints. 4. tested with gnd d v out d v cc . the device is disabled, i.e., ce 1 = v cc , ce 2 = gnd. 5. a series of normalized curves is available to supply the designer with typical dc and ac parametric information for logic devices static rams. these curves may be used to determine device characteristics at various temperatures and voltage levels. 6. tested with all address and data inputs chang- ing at the maximum cycle rate. the device is con- tinuously enabled for reading, i.e., ce 1 d v il , ce 2 t v ih , we t v ih, with outputs disabled, oe t v ih . input pulse levels are 0 to 3.0 v. 7. tested with outputs open and all address and data inputs stable. the device is continuously disabled, i.e., ce 1 t v ih , ce 2 d v il . 8. tested with outputs open and all address and data inputs stable. the device is continuously disabled, i.e. ce 1 = v cc , ce 2 = gnd. input levels are within 0.2 v of v cc or gnd. 9. data retention operation requires that v cc never drop below 2.0v. ce 1 must be t v cc - 0.2 v or ce 2 must be d 0.2 v. all other inputs must meet v in t v cc - 0.2 v or v in d 0.2 v to ensure full powerdown. for low power version if applicable , this requirement applies only to ce 1 , ce 2 , and we; there are no restrictions on data and address. 10. these parameters are guaranteed but not 100% tested. 11. test conditions assume input transition times of less than 3 ns, reference levels of 1.5 v, output loading for specified i ol and i o h plus 30 pf fig. 1a , and input pulse levels of 0 to 3.0 v fig. 2 . 12. each parameter is shown as a minimum or maximum value. input requirements are speci- fied from the point of view of the external system driving the chip. for example, t avew is specified as a minimum since the external system must supply at least that much time to meet the worst- case requirements of all parts. responses from the internal circuitry are specified from the point of view of the device. access time, for example, is specified as a maximum since worst-case operation of any device always provides data within that time. 13. we is high for the read cycle. 14. the chip is continuously selected ce 1 low, ce 2 high . 15. all address lines are valid prior-to or coinci- dent-with the ce 1 and ce 2 transition to active. 16. the internal write cycle of the memory is defined by the overlap of ce 1 and ce 2 active and we low. all three signals must be active to initiate a write. any signal can terminate a write by going inactive. the address, data, and control input setup and hold times should be referenced to the signal that becomes active last or becomes inactive first. 17. if we goes low before or concurrent with the latter of ce 1 and ce 2 going active, the output remains in a high impedance state. 18. if ce 1 and ce 2 goes inactive before or con- current with we going high, the output remains in a high impedance state. 19. powerup from i cc2 to i cc1 occurs as a result of any of the following conditions: a. rising edge of ce 2 ce 1 active or the falling edge of ce 1 ce 2 active . b. falling edge of we ce 1 , ce 2 active . c. transition on any address line ce 1 , ce 2 , active . d. transition on any data line ce 1 , ce 2 , and we active . the device automatically powers down from i cc1 to i cc2 after t pd has elapsed from any of the prior conditions. this means that power dissipation is dependent on only cycle rate, and is not on chip select pulse width. 20. at any given temperature and voltage con- dition, output disable time is less than output enable time for any given device. 21. transition is measured 200 mv from steady state voltage with specified loading in fig. 1b. this parameter is sampled and not 100% tested. 22. all address timings are referenced from the last valid address line to the first transitioning address line. 23. ce 1 , ce 2 , or we must be inactive during address transitions. 24. this product is a very high speed device and care must be taken during testing in order to real- ize valid test information. inadequate attention to setups and procedures can cause a good part to be rejected as faulty. long high inductance leads that cause supply bounce must be avoided by bringing the v cc and ground planes directly up to the contactor fingers. a 0.01 f high fre- quency capacitor is also required between v cc and ground. to avoid signal reflections, proper terminations must be used. +5 v output r 1 480 30 pf r 2 255 including jig and scope <3 ns gnd +3.0 v 90% 10% 90% 10% <3 ns +5 v output 5 pf including jig and scope r 1 480 r 2 255 figure 1a. figure 1b. figure 2
logic devices incorporated reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant informa- tion before placing orders and should verify that such information is current and complete. logic devices does not assume any l iability arising out of the application or use of any product or circuit described herein. in no event shall any liability exceed the product purcha se price. products of logic devices are not warranted nor intended to be used for medical, life support, life saving, critical control or safety appl ications, unless pursu- ant to an express written agreement with logic devices. furthermore, logic devices does not authorize its products for use as c ritical compo- nents in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. logic devices incorporated www.logicdevices.com aug 11, 2010 lds-L7C108/9-f 1m static rams 15 128k x 8 static ram L7C108 preliminary information l7c109 revision history L7C108/l7c109 revision engineer issue date description of change a b c d e f com m dh/ m dh m dh 10/8/2008 10/30/2008 07/02/2009 06/11/10 07/30/10 08/11/10 initial release datasheet format revision updated specs: 1. added 10ns & 12 speed columns in icc1 table 2. added 10ns speed and ac specs in the ac table 3. updated all dc power specs in dc table 4. corrected symbol names in ac and timing diagrams 5. added speed bin to ordering info table 6. removed commercial temp offering 7. added an extended temp offering revisions: 1. removed 10 & 12ns bins 2. removed 32ld fp to be re-introduced wiht our silicon, if market warrants 3. removed so package variant a 4. add notation for smd 5962-89598 that package will be supplied as a 7 compatible package 5. increased icc1, icc2, and icc4@2v for standard power 6. increased icc2 and icc4@2v for low power 7. removed appropriate dscc and logic part numbers from ordering tables and pn generator 8. modified logic devices a package reference to 9. corrections to package dimensions for md-k11 and md- 1 updated mechanical drawings for all packages revisions: 1. removed all 108 ka quad lcc and k dual lcc package variants from smd cross reference table. 2. updated order information chart to reflect current package availabilities. 3. changed icc2 conditions to match icc3 conditions. 4. changed operating current to be calculated during the read cycle.

▲Up To Search▲

Price & Availability of L7C108

	To Download L7C108 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .